1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a portion thereof concerning differential amplify operation.
2. Description of the Background Art
A semiconductor memory device, particularly a dynamic random access memory (referred to as DRAM hereinafter), is provided with a circuit for differential-amplifying the potential difference between a pair of bit lines generated by charge-read out from a memory cell to the bit line pair.
FIG. 15 is a circuit diagram showing a structure of a conventional semiconductor memory device, a DRAM in particular. This semiconductor memory device is formed on a semiconductor substrate 100. A memory cell 1 is connected to one of a pair of bit lines BL and /BL, for example to bit line BL. Memory cell 1 includes a capacitor 1C for storing data and an N channel MOS transistor (NMOS transistor) 1T. NMOS transistor 1T is connected between capacitor 1C and bit line BL. The gate thereof is connected to a word line WL.
Between bit line pair BL and /BL, a first sense amplifier SA1 which is the first differential amplify means, a second sense amplifier SA2 which is the second differential amplify means, and an equalizer EQ which is the precharge means are connected.
First sense amplifier SA1 includes NMOS transistors 4, 5, and 12. NMOS transistors 4 and 5 are connected in series between bit line pair BL, /BL. NMOS transistors 4 and 5 have their sources connected to each other, and their drains connected to bit line BL and bit line /BL, respectively. NMOS transistor 4 has its gate connected to bit line /BL, and NMOS transistor has its gate connected to bit line BL. This connection implements cross coupled NMOS transistors 4 and 5.
NMOS transistor 12 is connected between an outgoing line node Z which is the node between NMOS transistors 4 and 5 and a ground node 11 receiving ground potential GND. The gate of NMOS transistor 12 is applied with a sense operation activating signal SON.
Second sense amplifier SA2 includes P channel MOS transistors (referred to as PMOS transistor hereinafter) 6, 7 and 14. PMOS transistors 6 and 7 are connected in series between bit line pair BL and /BL. PMOS transistors 6 and 7 have their sources connected to each other, and their drains connected to bit line BL and bit line /BL, respectively. PMOS transistors 6 and 7 have their gates connected to bit lines /BL and BL, respectively. Such a connection implements cross coupled PMOS transistor 6 and 7.
A PMOS transistor 14 is connected between a supply line node Y which is the node between PMOS transistors 6 and 7 and a power supply node 13 receiving power supply potential VCC. The gate of PMOS transistor 14 is applied with a sense operation activating signal SOP.
Equalizer EQ includes NMOS transistors 8, 9 and 10. NMOS transistor 8 is connected between the pair of bit lines BL and /BL. NMOS transistor 9 is connected between bit line BL and a potential node Vpr receiving a potential of 1/2 the power supply potential VCC. NMOS transistor 10 is connected between bit line /BL and potential node Vpr. Each gate of NMOS transistors 8, 9 and 10 is applied with a precharge activating signal BLEQ.
An NMOS transistor 15 is connected between outgoing line node Z and potential node Vpr. An NMOS transistor 16 is connected between supply line node Y and potential node Vpr. Each gate of NMOS transistors 15 and 16 is applied with a precharge activating signal BLEQ.
On bit line pair BL and /BL, NMOS transistors 2 and 3 for connecting first and second sense amplifiers SA1 and SA2 and equalizer EQ with memory cell 1 are provided between memory cell 1, and first and second sense amplifiers SA1, SA2 and equalizer Q. NMOS transistor 2 is provided at bit line BL and NMOS transistor 3 is provided at bit line /BL. NMOS transistors 2 and 3 are activated by activating signal BLI.
The operation of a semiconductor memory device of the above-described structure is described hereinafter. In a standby state (precharge state) of this device, bit line pair BL, /BL, outgoing line node Z, and supply line node Y are precharged to a potential of 1/2 VCC (referred to as precharge potential hereinafter).
Precharge is effected by precharge activating signal BLEQ attaining a high level to activate NMOS transistors 8, 9, 10, 15 and 16. More specifically, precharge is carried out by respective short-circuits between bit line pair BL, /BL and potential node Vpr, between outgoing line node z and potential node Vpr, and between supply line node Y and potential node Vpr.
A data read out operation from memory cell 1 is described hereinafter. In a read out operation, data is transmitted from memory cell 1 to bit line BL, followed by an amplify operation by first and second sense amplifiers.
FIG. 16 is a signal waveform diagram of each component in circuitry at the time of a read out operation. Read out operation will be described with reference to FIG. 12.
When stabilization of the above-described precharge state is achieved, precharge activating signal BLEQ is pulled down to a low level, whereby NMOS transistors 8, 9, 10 and 11 are inactivated. As a result, the pair of bit lines BL, /BL attain a floating status at precharge potential.
When word line WL is activated to have potential VBL raised, charge representing data stored in memory cell 1 is transmitted on bit line BL. This is the transmission operation of data. If memory cell 1 stores data "1", for example, potential VBL of bit line BL becomes slightly higher than the precharge potential. Bit line /BL remains at the precharge potential. Therefore, there is a slight potential difference between bit lines BL and /BL.
When such a potential difference is generated, this potential difference is amplified by the amplify operation of first and second sense amplifiers SA1 and SA2. In the amplify operation, first an amplification by the first amplifier SA1 is carried out. Sense operation activating signal SON is activated to attain a high level, whereby NMOS transistor 12 is activated. This causes shorting between outgoing line node Z and ground node 11, whereby potential VZ of outgoing line node Z is decreased towards ground potential GND.
As a result, NMOS transistors 4 and 5 have their gate-source voltages increased to be activated. When NMOS transistors 4 and 5 are activated, the on resistance of NMOS transistor 5 becomes lower than that of NMOS transistor 4 due to potential VBL of bit line BL being higher than potential V/BL of bit line /BL, whereby potential V/BL of bit line /BL is reduced.
Next, amplification by second sense amplifier SA2 is carried out. Sense operation activation signal SOP is activated to attain a low level, whereby PMOS transistor 14 is activated. This causes shorting between supply line node Y and power supply node 13, whereby potential VY of supply line node Y is increased towards power supply potential Vcc.
As a result, PMOS transistors 6 and 7 have their gate-source voltages increased to be activated. When PMOS transistors 6 and 7 are activated, the on resistance of PMOS transistor 6 becomes smaller than that of PMOS transistor 7 due to potential V/BL of bit line /BL being lower than potential VBL of bit lines BL. Therefore potential VBL of bit line BL increases.
Then, potential V/BL of bit line /BL is reduced to the level of ground potential GND, and potential VBL of bit line BL is increased to the level of power supply potential VCC. By the above-described amplify operation, a slight potential difference between bit lines BL and /BL is amplified to a greater level.
At the start of an amplify operation, the source potentials of NMOS transistors 4 and 6 attain a precharge potential, as described above. The substrate potential is generally ground potential GND or lower thereof, i.e. a potential lower than the source potential. Therefore, NMOS transistors 4 and 6 are subjected to a body effect at the start of an amplify operation, whereby each threshold voltage becomes higher than the case where the threshold value of a transistor has equal substrate potential and source potential.
The reason thereof is set forth in the following. FIG. 17 is a graph showing the relationship between a substrate potential and a threshold voltage by a solid line. The threshold voltage is plotted along the ordinate, and the substrate potential is plotted along the abscissa (the potential decreases in the right direction).
It is apparent from FIG. 17 that the threshold voltage increases according to a reduction of the substrate potential with respect to the source potential. For example, the threshold voltage at a substrate potential of VN which is a potential where the source potential equals the substrate potential is lower than the threshold voltage at a substrate potential of VE which is a potential where the substrate potential is lower than the source potential, as indicated by the broken line in the graph.
Although the graph of FIG. 17 relates to an NMOS transistor, the same holds for a PMOS transistor provided that the polarity of the potential between the source potential and the substrate potential differs.
When the absolute value of a threshold voltage of a MOS transistor increases due to a body effect, a problem occurs as set forth in the following.
In response to the demand of reducing the size of a semiconductor memory device, a trend is towards lowering the power supply potential of the device. In response to such a reduction in power supply potential, the precharge potential which is 1/2 the power supply potential is also reduced. When the absolute value of a threshold voltage in a MOS transistor of a sense amplifier is increased due to a body effect in the case where precharge potential is reduced, the difference between the precharge potential and the threshold voltage becomes smaller. This reduction in the difference between a precharge potential and a threshold voltage results in problems such as reduction in the sense operation speed of a sense amplifier or the sense amplifier not operating.
Because a MOS transistor is also used in an equalizer as well as in a sense amplifier in a semiconductor memory device, reduction in the power supply potential will lead to the possibility of malfunction in the equalizer by reasons identical to those of a sense amplifier. A predetermined precharge potential level cannot be achieved if malfunction occurs in an equalizer, and margin of the sense operation of a sense amplifier is reduced. This margin reduction results in a problem that the speed of sense operation is reduced or that the sense amplifier is not operated.
In addition to the above-described problems caused by a body effect, reduction of a power supply potential causes problems as set forth in the following.
FIGS. 18(A) and 18(B) are graphs showing the relationship between a gate-source voltage of a general MOS transistor and current flowing therein. Logarithm of current is plotted along the ordinate, and the gate-source voltage is plotted along the abscissa. In the graphs, the gate-source voltage applying a current of a predetermined value (in this embodiment, 10.sup.-6 A) to the MOS transistor represents threshold voltage.
The relationship between a gate-source voltage and a current in a MOS transistor generally has the characteristics shown in FIG. 18(A). More specifically, in a region of the gate-source voltage that is below the threshold voltage (referred to as sub-threshold region hereinafter), the current increases according to increase in the gate-source voltage. If the gate-source voltage exceeds the threshold voltage, the current is saturated at a predetermined value. If the aforementioned body effect works greatly, current will not easily flow in the MOS transistor, whereby the characteristics vary in the direction indicated by the arrow. As a result, the gate-source voltage increases at a current value corresponding to the threshold voltage to cause increase in the threshold voltage.
In a MOS transistor having the characteristics shown in FIG. 18(A), the gradient of the characteristic curve in the sub-threshold region become more gentle when voltage is applied to the drain as shown in FIG. 18(B) in proportion to reduction in the threshold voltage. This reduction in the inclination of the characteristic curve results in a greater current value when the gate-source voltage is 0 V. Increase in a current value means that the leak current in a MOS transistor is increased.
Thus, because leak current increases as the threshold voltage is reduced in a MOS transistor, a semiconductor memory device having power supply potential reduced and set with a lower value of threshold voltage will encounter increase in leak current in the MOS transistor of a sense amplifier. This leads to a problem that the potential of a bit line after amplification by a sense amplifier is deviated from a predetermined stable value in a semiconductor memory device.
As described above, a conventional semiconductor memory device had a problem that stabilization of operation cannot be achieved due to reduction in the power supply potential. A semiconductor memory device solving such a problem is disclosed in Japanese Patent Laying-Open No. 2-231760. This semiconductor memory device has the well potential of a MOS transistor forming a sense amplifier varied according to a change in the source potential of that MOS transistor. The body effect is suppressed by varying the well potential of a MOS transistor according to a change in the source potential, whereby the operation of the sense amplifier is stabilized.
However, the semiconductor memory device disclosed in Japanese Patent Laying-Open No. 2-231760 had problems set forth in the following. Although this semiconductor memory device can have a body effect of a MOS transistor forming a sense amplifier suppressed, reduction in the operation speed of a sense operation could not be compensated for when the power supply potential of a semiconductor memory device is reduced significantly and the difference between the precharge potential and the threshold voltage of a MOS transistor is reduced significantly.
This semiconductor memory device can achieve stabilization of the operation of a sense amplifier, but does not solve unstabilization of the operation of an equalizer in accordance with reduction in the power supply potential.
Furthermore, although such a semiconductor memory device can achieve stabilization in the operation of a sense amplifier at the start of a sense operation, it cannot solve unstabilization of the potential of a bit line pair after amplification by a sense amplifier.
Since a semiconductor memory device disclosed in Japanese Patent Laying-Open No. 2-231760 also had various problems as described above, there is still the problem of unstabilization of operation according to reduction of the power supply potential not sufficiently prevented in a conventional semiconductor memory device.